Variable width pulse generator



Dec. 19, 1967 WY 5. HARRIS VARIABLE WIDTH PULSE GENERATOR Filed May 28,1964 2 Sheets-Sheet 1 FIG.

( UT/L/ZAT/ON CONTROL CIRCUIT D. C. SOURCE SCR,

//Vl/E/VTOR By W 8. HA RR/S ATTORNEY United States Patent 3,359,498VARIABLE WIDTH PULSE GENERATOR William B. Harris, Bernardsville, N.J.,assignor to Bell Telephone Laboratories, Incorporated, New York, N.Y., acorporation of New York Filed May 28, 1964, Ser. No. 370,934

Claims. (Cl. 328-57) ABSTRACT OF THE DISCLOSURE A variable width pulsegenerator includes first and second controlled rectifiers and a tunedcircuit connected with a load across a source of constant potential.Current flows through the load for the full period of the tuned circuitless the time between the closing of the second and the firstrectifiers. The operation is due to circulating currents initiated inthe tuned circuit when the second rectifier is closed. The circulatingcurrents open the second rectifier at the end of one-half period of thetuned circuit and open the later closed first rectifier at the end ofthe full period. Various embodiments are described.

This invention relates to pulse generators, and, more particularly, topulse generators of the type supplying pulses of variable durations.

Frequently, pulse generating circuits include a con trolled switch suchas a silicon controlled rectifier connected electrically in series witha load across which an output is developed. Such a switch isconveniently closed and opened, respectively, for initiating andterminating current through the load. Often, a pulse generator whichincludes such a switch also includes a tuned circuit which operates inresponse to the closing of the switch to open the switch at a fixed timethereafter thus terminating the pulse through the load. This fixed timeis equal, esssentially, to one half the period of the tuned circuit andmay be varied by changing the capacitance and/or the inductance of thetuned circuit. The use of tuned circuits in this connection is discussedin the July 1963 issue of Electronic Engineering, at page 470 et seq.

For some circuit applications such as in certain pulse testing circuitsand in radar applications, it is advantage ous to provide pulses ofdifferent durations without changing the capacitance and/or theinductance of such a tuned circuit. Moreover, it is frequentlydesirable, for example, in radar applications, to produce high powerpulses across a load. To this end, it is desirable to employ a lowimpedance source and to employ switching elements which also arecharacterized by low impedances in order to avoid losses therein.Although silicon controlled rectifiers are well suited as switches insuch circuits, difficulties are encountered therewith in turning allhigh current pulses.

Accordingly, a prime object of this invention is to provide a new andnovel pulse generator capable of delivering pulses of controllablydifferent durations.

Another object of this invention is to provide a pulse generator capableof producing, with little loss, high power pulses across a load.

The above and further objects of this invention are realized in oneembodiment thereof wherein first and second silicon controlledrectifiers are connected electrically in series with a load across asource of constant electric potential. The second rectifier is furtherconnected electrically in parallel with a serial arrangement of aninductor and a capacitor forming a tuned circuit, and, also, with adiode poled in a direction opposite to that in which the secondrectifier is poled. In this connection the term poled in a directionopposite indicates that the diode and the rectifier are connected,individually, to pass current in directions opposite to one another. Inresponse to the "ice closing of the second rectifier, circulatingcurrents are initiated in the tuned circuit. These currents operate toopen the second rectifier at the end of one half the period of the tunedcircuit and open the first rectifier at the end of the full period.Current flows through the load for a time equal to the full period ofthe tuned circuit less the time between closing the second and firstrectifiers which time may, conveniently, be fixed by external circuitry.Thus, the termination of the pulse through the load is at a time fixedby the closing of one rectifier. The time of the initiation of thepulse, however, is fixed, independently, by the closing of anotherrectifier.

In another embodiment of this invention, a first silicon controlledrectifier, connected electrically in series with a load across a sourceof constant electric potential, is also connected electrically inparallel with a series arrangement of a second silicon controlledrectifier shunted by an oppositely poled diode, and an inductor and acapacitor forming a tuned circuit. Current flow through the load isinitiated by closing the first rectifier; the current flow isterminated, at a time equal to the full period of the tuned circuitafter the second rectifier is closed, by currents circulating in thetuned circuit in response to the closing of the second rectifier. Again,times for the initiation and termination of a pulse through a load arefixed independently by different rectifiers.

Accordingly, a feature of this invention is first and second controlledrectifiers for controllably fixing the duration of current flowingthrough a load.

Another feature of an embodiment of this invention is a tuned circuitcooperating with the first and second controlled rectifiers to open thecontrolled rectifiers at different times in response to the closing ofthe second rectifier.

The invention and the further objects and features thereof will beunderstood more fully with reference to the following descriptionrendered in connection with the accompanying drawing in which:

FIG. 1 is a schematic representation of a first embodiment of thisinvention;

FIG. 2 is a pulse diagram showing the control pulses for closing andopening the rectifiers in the circuit of FIG. 1 and the current flowingthrough the load resistance in response thereto;

FIG. 3 is a modified portion of the circuit of FIG. 1;

FIG. 4 is a schematic representation of a second embodiment of thisinvention;

FIG. 5 is a schematic representation of a modification of the circuit ofFIG. 4; and 7 FIG. 6 is a pulse diagram showing the control pulsesfor-closing and opening the rectifiers in the circuit of FIG. 4 and thecurrent flowing through the load resistance in response thereto.

FIG. 1 shows a circuit 10 in accordance with this invention. The circuitcomprises a basic arrangement of a load resistance R and first andsecond silicon controlled rectifiers SCR andSCR connected electricallyin series across a low impedance direct current source of constantelectric potential 11. Each rectifier includes an anode, a cathode, anda gate electrode designated A, C, and G, respectively. The lowerconnection to the source 11, as viewed in the figure, is electrically atground potential. The second rectifier, SCR has connected, electricallyin parallel therewith, a serial arrangement of an inductor 12 and acapacitor 13, forming a tuned circuit TC and, electrically in parallelthereacross, a diode 14. Rectifier SCR is poled in the same direction asrectifier SCR to permit current to flow from source 11 through loadresistance R;,, through the two rectifiers to ground, when both of therectifiers are conducting, or, in other words, closed. Diode 14 is poledin a direction opposite to that of rectifier SCR A voltage dividernetwork of three resistances R R and R is connected electrically inparallel across both rectifiers SCR and SCR Each of the rectifiers isprovided gate circuitry. For clarity, however, only the gate circuitryfor rectifier SCR is shown; the gate circuitry for rectifier SCR may be,but is not necessarily, the same. Specifically, the gate circuitry G forrectifier SCR comprises a first circuit including a series arrangementof a gate resistance R a capacitor 15, and the secondary of atransformer T, electrically in parallel with resistance R connectedbetween the gate electrode of the rectifier SCR and a point P in thecircuit between the two rectifiers SCR and SCR The gate circuitry G alsocomprises a second circuit including the primary of the transformer Tconnected be tween a control circuit 16 and ground. The gate circuitry Gis represented by a conductor designated G from the gate electrode ofrectifier SCR to a terminal of control circuit 16. The conductor isshown including only the gate resistance R A utilization circuit 17 isconnected across the load resistance R In this connection, theutilization circuit may be any circuit capable of using a pulsedeveloped across load resistance R in accordance with this invention.Control circuit 16 is connected to the source 11 and to the utilizationcircuit 17 via conductors 18 and 19, respectively.

In the operation of the circuit of FIG. 1 in accordance with thisinvention, source 11 is turned on and capacitor 13 in tuned circuit TCis charged to the voltage of source 11 through rectifier SCR closedunder the control of control circuit 16, specifically to this end. Aswill become apparent hereinafter, capacitor 13, in practice, is in acharged condition at the termination of each pulse provided through loadresistance R in readiness for a subsequent operation. In thisconnection, source 11 and control circuit 16 may be any source andcircuit, respectively, capable of performing in accordance with thisinvention. Rectifier SCR opens when current therethrough drops below thesustaining level. After rectifier SCR opens, the current through loadresistance R becomes insignificant. -In this connection, the values ofresistances R R and R are chosen high to permit the passage of only anegligible current therethrough.

Then, rectifier SCR is closed by a gate pulse under the control ofcontrol circuit 16 at a time designated t in FIG. 2. In this connection,FIG. 2 shows a plot of current versus time for the current through theload resistance. Also shown in FIG. 2 are the gate pulses for rectifiersSCR and SCR the latter superimposed on the waveform for the circulatingcurrent through inductor 12 and capacitor 13 during what is commonlytermed the period of the tuned circuit. At a time less than the periodof the tuned circuit after the closing of rectifier SCR rectifier SCR isclosed also by a gate pulse under the control of control circuit 16.This time is designated t in FIG. 2. For this purpose, the gate pulsesare of short duration, typically 1.0 microsecond. The closing ofrectifier SCR initiates significant current flow i through the loadresistance R if SCR is already closed. The prior closing of rectifierSCR however, initiates circulating currents in tuned circuit TC whichopens SCR and SCR at fixed times after the closing of SCR Specifically,upon closing rectifier SCR circulating currents arise from the dischargeof capacitor 13 and result in the charging of inductor 12 during what iscommonly termed the first half period of the tuned circuit. During thesecond half period of the tuned circuit, current is directed from theinductor 12 back into the capacitor 13. At the onset of this second halfperiod, designated i in FIG. 2, SCR is opened by the reversal of thecirculating currents. The upper plate of capacitor 13 (as viewed inFIG. 1) at this time is charged negative by the circulating currents andthe current flowing through the load resistance, requiring the lowerplate thereof to accumulates a positive charge. Capacitor 13,thereafter, discharges through diode 14. The current i;,

flowing through the load resistance R also flows through diode 14 untilthe positive charge on the lower plate of capacitor 13 is exhausted, atwhich time, designated t in FIG. 2, current flow through diode 14 stops,rectifier SCR is opened, consequently, and current flow i through theload resistance ceases.

It is thus shown that, in response to the closing of the secondrectifier SCR circulating currents are initiated in the tuned circuitTC. These circulating currents open the second rectifier SCR at,essentially, the half period of the tuned circuit, and open the firstrectifier SCR essentially, at the end of the full period of the tunedcircuit. In this manner, current flow through the load is terminated ata time essentially equal to the full period of the tuned circuit afterrectifier SCR is closed.

It is also shown that current through the load resistance is initiated,independent of the termination time thereof, by closing the firstrectifier SCR if, and only if, the second rectifier .SCR has alreadybeen closed. Accordingly, current flows through the load resistance fora time equal to, essentially, the full period of the tuned circuit lessthe time between closing the second and the first rectifiers. Since theclosing of the rectifiers is via gate pulses under the control ofcontrol circuit 16, the circuit of FIG. 1, thus, controllably providescurrent pulses having durations equal to, essentially, the period of thetuned circuit or less. This corresponds to a range of, typically, 30microseconds to about 1.0 microsecond.

The current flowing through resistances R R and R provides a negativebias on the gate of SCR when both rectifiers are open. When rectifierSCR is closed, the anode electrode of rectifier SCR is essentiallygrounded and the negative bias provided through resistance R is lost.Also, when rectifier SCR is closed, the high rate of change of voltagewith respect to time (dv/at) thereacross, characteristic of suchrectifiers, tends to close, prematurely, rectifier SCR The voltageacross capacitor 15, however, maintains the bias on the gate ofrectifier SCR for a sufficient time thereafter to avoid prematureclosing of rectifier SCR In the circuit of FIG. 1 current flow throughload resistance R was described as terminating when the positive chargeon the lower plate of capacitor 13 is exhausted through diode 14.Actually, current flow through the load resistance continues slightlybeyond this juncture to again recharge capacitor 13 to its initialcondition. This recharging of the capacitor determines the decay timefor the current i through the load resistance as shown by the trailingedge of the pulse i in FIG. 2. The actual shape of the decay, of course,depends on the value of the resistance R and the values of theinductance and capacitance of elements 12 and 13, respectively. For anygiven values of load resistance and inductance and capacitance, however,the decay can be made distinctly sharper, for example, from a typicaldecay time of about 20 microseconds, by a factor of 10 to 2microseconds, in accordance with the modification of the circuit of FIG.1 as shown in FIG. 3. The improvement in decay time is illustrated bythe broken trailing edge of pulse i in FIG. 2.

Since FIG. 3 is a modification of circuit 1, only as much of circuit 1as is necessary for an orientation of the modification therein is shown.Furthermore, those elements of FIG. 1 shown in FIG. 3 are given the samedesignations there as in FIG. 1 and will not be discussed further.Specifically, in accordance with this modification the anode electrode Aof an additional silicon controlled rectifier SCR is connected betweenthe source 11 and the load resistance R the cathode C and the gate Gelectrodes of the rectifier SCR with a resistance R, between them areconnected between diode 14 and inductor 12. The gate circuit ofrectifier SCR also includes a resistance R In operation, when thedischarge of capacitor 13 through diode 14 is complete, current startsto flow through diode 14 in the reverse direction for a brief perioduntil diode 14 is reverse biased. This current flow through resistance Ris sutficient to gate rectifier SCR in (closed) permitting therecharging of capacitor 13 through rectifier SCR rather than through theload. In this manner, the current through the load resistance decaysmore sharply than in accordance with the circuit of FIG. 1.

The circuit of FIG. 1, as was stated hereinbefore, provides variablewidth pulses with a maximum duration essentially that of the period ofthe tuned circuit. For many applications, however, pulses of longerduration are required. Such pulses are provided, in accordance with thisinvention, by the circuit of FIG. 4.

Specifically, FIG. 4 shows a circuit 110 in accordance with thisinvention. The circuit comprises a basic arrangement of a loadresistance R;, and a first silicon controlled rectifier SCR connected inseries across a low impedance direct current source of constant electricpotential 111. The lower connection, as viewed in the figure, iselectrically at ground potential. A diode 112 is connected electricallyin parallel with the rectifier SCR; and poled oppositely thereto. Aseries arrangement of a second silicon controlled rectifier SCR aninductor 113 and a capactior 114 is also connected electrically inparallel with the rectifier SCR Thus a tuned circuit TC is formed. Therectifiers SCR. and SCR are poled in opposite directions. A diode 115 isconnnected electrically in parallel with SCR and poled oppositelytherefrom as shown in FIG. 4. Both rectifiers SCR and SCR may beconnected by like gate circuitry. Only the gate circuitry G 'forrectifier SCR is shown, however. Specifically, the gate electrode G ofrectifier SCR is connected to a common point P between rectifiers SCRand SCR through the secondary of a transformer T and a gate resistance RThe primary is connected between ground and a control circuit 116 at aterminal designated G The gate circuitry for rectifier SCR isrepresented by a conductor designated G including only gate resistance Rconnected to a terminal G of control circuit 116. A utilization circuit117 is connected across the load resistance R Control circuit 116 isconnected to source 11 and utilization circuit 117 via conductors 118and 119, respectively. Pulse source 111, control circuit 116, andutilization circuit 117 may be any circuit elements capable ofperforming in accordance with this invention.

In operation, source 111 is turned on, and capacitor 114 is initiallycharged to the source potential via diode 115. (As will become apparenthereinafter, the capacitor is in a charged condition at the terminationof a previous pulse.) Thereafter, at a time designated t in FIG. 6,rectifier SCR is closed via gate circuitry G under the control ofcontrol .circuit 116. The closing of rectifier SCR; provides a currentpath to ground, and, consequently, current flows through load resistanceR for any desired length of time. Thereafter, at an arbitrary timedesignated t in FIG. 6, rectifier SCR is closed via 'a pulse in gatecircuitry G under the control of control circuit 116 thus initiatingcirculating currents through inductor 113 and capacitor 114. Thecirculating current is represented by the sine wave in FIG. 6.Specifically, in response, to the closing of rectifier SCR capacitor 114discharges through rectifiers SCR and SCR charging inductor 113 duringthe first half period of the tuned circuit. At the onset of the secondhalf 112 until the charge on capacitor 114 is exhausted, current ithrough load resistance R terminating at a time,

6 designated 1 in FIG. 6, equal, essentially, to the full period of thetuned circuit after the closing of rectifier SCR FIG. 5 shows a circuit210, in accordance with this invention, which is quite similar to thecircuit of FIG. 4. Specifically, a load resistance R and a siliconcontrolled rectifier SCR are connected in series across a direct currentsource of constant electric potential 211, the lower connection, asviewed in the figure being at ground potential. The rectifier SCR isconnected electrically in parallel with a branched network including, inone branch, a diode d poled in a direction opposite to that of rectifierSCR in the second branch, a second silicon controlled rectifier SCRpoled in the same direction as rectifier SCR and, in a third branch, 9.series arrangement of an inductor 212 and a capacitor 213 forming atuned circuit TC. In addition, a resistance R; is connected electricallyin series with the diode d; and a resistance r, is connectedelectrically in parallel with inductor 212. A diode d is connectedbetween the two rectifiers SCR and SCR poled in the direction ofrectifier SCR A utilization circuit 214 is connected across loadresistance R The source 211 and utilization circuit 214 are connected toa control circuit 215 via conductors 216 and 217, respectively. Theanode and gate electrodes A and G, respectively, of a third siliconcontrolled rectifier SCR are connected across the load resistance, andthe cathode electrode C thereof is connected between resistance R anddiode d The gate circuits of the various rectifiers are represented bybroken lines designated G and G for connection to control circuit 215 atterminals G and G there. The circuits, however, are not otherwiseillustrated.

In operation, the circuit of FIG. 5 performs quite similarly to that ofFIG. 4. Specifically, current flow through the load resistance R isinitiated by closing rectifier SCR, under the control of control circuit215. Current flow through the load resistance R is terminated by closingrectifier SCR at a time equal to, essentially, the period of the tunedcircuit TC prior to the desired termination time. In response to theclosing of rectifier SCR the circuit responds substantially as describedin connection with the circuit of FIG. 4 except that the two rectifiersSCR and SCR are turned off in parallel at the termination of, the firsthalf period of the tuned circuit TC rather than being turned off inseries as is the mode in accordance with the circuit of FIG. 4.

With the circuit of FIG. 5, a high frequency oscillation occurs acrossinductor 212 when rectifier SCR is closed. This oscillation issuperimposed on the voltage of capacitor 213 and may be of sufficientamplitude to activate SCR before it is gated closed. This high frequencyoscillation is caused by the sudden'application of the capacitor voltageacross inductor 212 and has a frequency approximately equal to theresonant frequency of the inductor 212 and the capacitance of diode dThis oscillation is eliminated, essentially, by a resistance R,, acrossinductor 212, of the value to critically or slightly overdamp theinductor at the oscillation frequency.

The rectifier SCR is employed, optionally, to provide a bypass acrossthe load resistance R for recharging capacitor 213. In this manner, thecurrent through load resistance R decays sharply as described inconnection with FIG. 2 and is illustrated in relation to the embodimentof FIG. 5 as the broken trailing edge to the pulse i in FIG. 6.

In the various circuits in accordance with this invention, there is aconstant forward bias maintained by the source across certain rectifierstherein. For example, in FIG. 4 the source maintains a forward bias onrectifier SCR Such rectifiers are characterized by a reverse recoverytime, however. In this connection, the term reverse recovery time isdefined as the difference in time between the time when current is zeroin the rectifier and the time thereafter when forward voltage can againbe applied without closing the rectifier. Typically, this time is about10.0 microseconds. From a practical standpoint, this means that when arectifier is opened by the reversal of current therein in accordancewith this invention, that reversal is maintained for a time in excess ofthe recovery time of the rectifier. Consequently, the half period of atuned circuit in accordance with this invention is chosen in excess ofthe recovery time of the rectifiers used. For the circuit of FIG. 4,then, a minum pulse width is about 30 microseconds. This allows time forthe reversing current to reach a sufiicient amplitude to effectreversal. Any well known seriesparallel, inductor-capacitor,pulse-forming network may be substituted for the series inductor andcapacitor in circuit 4 for making relatively square, in Wave shape, thecurrent flowing through rectifier SCR, achieveing current reversal morequickly, and, consequently, permitting even narrower pulses with thiscircuit. For example, with a given recovery time for rectifier SCRcircuit 4 including such a pulse-forming network provides pulses withwidths as narrow as to microseconds rather than 30 microseconds.

In accordance with this invention, typical values for the source, theload resistance, the inductor, and the capacitor therein are 400 volts,20 ohms, 50 microhenries, and 0.5 microfarad, respectively. A typicalrepetition rate for a circuit in accordance with this invention iskilocycles. If higher source voltages are used, the rectifiers describedherein may be replaced each by a series of rectifiers.

No effort has been made to exhaust the possible embodiments of thisinvention. It will be understood that the embodiments described aremerely illustrative of the invention and various modifications may bemade therein without departing from the scope and spirit of theinvention.

What is claimed is:

1. A variable width pulse generator comprising first and secondcontrolled switches having first and second gate electrodes,respectively, said first and second switches being connected with a loadacross a source of substantially constant electric potential, meansincluding first and second gate means connected to said first and secondgate electrodes, respectively, for controllably closing said first andsecond switches in accordance with a timed sequence, a series tunedcircuit responsive to the closing of said second switch for controllablyopening said first and second switches and a normally reverse-biaseddiode shunting said series tuned circuit.

2. A variable width pulse generator in accordance with claim 1 whereinsaid first and second switches are connected in series.

3. A variable width pulse generator in accordance with claim 1 whereinsaid first and second switches are connected electrically in parallel.

4. A variable width pulse generator comprising first and secondcontrolled rectifiers having first and second gate electrodes,respectively, said first and second rectifiers being connected serially,in like polarity, with a load across a source of substantially constantelectric potential, means including first and second gate meansconnected to said first and second gate electrodes, respectively, forcontrollably closing the corresponding rectifiers in accordance with atimed sequence, and a tuned circuit responsive to the closing of saidsecond rectifier for opening said first and second rectifiers atdifierent times, said tuned circuit comprising a serial arrangement ofan inductor and a capacitor connected electrically in parallel with saidsecond rectifier, and a diode shunting said serial arrangement, saiddiode being poled in a direction opposite to the direction in which saidsecond rectifier is poled.

5. A variable width pulse generator including a load and first andsecond silicon controlled rectifiers connected electrically in seriesacross a source of substantially constant electric potential, said firstand second rectifiers being connected in like polarity and having firstand second gate electrodes respectively, tuned circuit means includingan inductor and a capacitor shunted by a diode and a resistance, saidtuned circuit means being connected electrically in parallel across saidsecond rectifier for opening, at different times, said second and thensaid first rectifiers in response to the closing of said secondrectifier, said tuned circuit having a definite period, first and secondgate means connected to said first and second gate electrodes,respectively, for controllably closing said second and first rectifiersin accordance with a timed sequence, means for initially charging saidcapacitor to a predetermined voltage, and means for recharging saidcapacitor at the termination of said period.

6. A variable width pulse generator comprising first and secondcontrolled rectifiers having first and second gate electrodesrespectively, said first and second rectifiers being connected serially,in like polarity, with a load across a source of substantially constantelectric potential, 'means including first and second gate meansconnected to said first and second gate electrodes, respectively, forcontrollably closing said first and second rectifiers in accordance witha timed sequence, a tuned circuit responsive to the closing of saidsecond rectifier for opening said first and second rectifiers atdifferent times, said tuned circuit comprising a first serialarrangement of an inductor and a capacitor connected electrically inparallel with said second rectifier, and a second serial arrangement ofa diode and a first resistance connected electrically in parallel withsaid first serial arrangement, said diode being poled in a directionopposite to the direction in which said second rectifier is poled, and athird rectifier, said third rectifier having gate, cathode, and anodeelectrodes, said anode being connected between said source and said loadresistance, and said gate and cathode being connected across said firstresistance.

7. A variable width pulse generator comprising a first controlledrectifier connected electrically in series with a load across a sourceof substantially constant electric potential, a second controlledrectifier, said first and second controlled rectifiers having first andsecond gate electrodes, respectively, means including first and secondgate means connected to said first and second gate electrodes,respectively, for closing said first and second rectifiers in accordancewith a timed sequence, and a tuned circuit responsive to the closing ofsaid second rectifier for opening said first and second rectifiers, saidtuned circuit including a serial arrangement of said second controlledrectifier, shunted by a first diode poled in a direction opposite tothat in which said second rectifier is poled, an inductor and acapacitor, and a second diode, said second diode being connected inshunt across said first rectifier and poled in a direction opposite thatin which said first rectifier is poled.

3. A variable width pulse generator comprising a first controlledrectifier connected electrically in series with a load across a sourceof substantially constant electric potential, second and thirdcontrolled rectifiers, said first, second and third controlledrectifiers having first, second and third gate electrodes, respectively,means including first and second gate means connected to said first andsecond gate electrodes, respectively, for closing said rectifiers inaccordance with a timed sequence, a branched network connectedelectrically in parallel with said first controlled rectifier, saidbranched network comprising a first branch including a serialarrangement of a first resistor and a first diode poled in a directionopposite to that of said first rectifier, a second branch including saidsecond controlled rectifier poled in the same direction as said firstcontrolled rectifier, and a third branch including a serial arrangementof an inductor and a capacitor, a second diode connected between saidfirst and second branches, said second diode being poled in the samedirection as said second rectifier, said third controlled rec- 9 tifierhaving anode and cathode electrodes, the anode and gate electrodes ofsaid third rectifier being connected across said load resistance, thecathode electrode of said third rectifier being connected between saidfirst resistor and said first diode.

9. A variable width pulse generator in accordance with claim 8 whereinsaid third branch includes a resistance electrically in parallel withsaid inductor therein.

10. A variable width pulse generator comprising first and secondcontrolled switches having first and second gate electrodesrespectively, said first and second switches being connected in serieswith a load across a source of substantially constant electricpotential, means including first and second gate means connected to saidfirst and References Cited UNITED STATES PATENTS 2,916,640 12/1959Pearson 32867 ARTHUR GAUSS, Primary Examiner.

B. P. DAVIS, Assistant Examiner.

1. A VARIABLE WIDTH PULSE GENERATOR COMPRISING FIRST AND SECONDCONTROLLED SWITCHES HAVING FIRST AND SECOND GATE ELECTRODES,RESPECTIVELY, SAID FIRST AND SECOND SWITCHES BEING CONNECTED WITH A LOADACROSS A SOURCE OF SUBSTANTIALLY CONSTANT ELECTRIC POTENTIAL, MEANSINCLUDING FIRST AND SECOND GATE MEANS CONNECTED TO SAID FIRST AND SECONDGATE ELECTRODES, RESPECTIVELY, FOR CONTROLLABLY CLOSING SAID FIRST ANDSECOND SWITCHES IN ACCORDANCE WITH A TIMED SEQUENCE, A SERIES TUNEDCIRCUIT RESPONSIVE TO THE CLOSING OF SAID SECOND SWITCH FOR CONTROLLABLYOPENING SAID FIRST AND SECOND SWITCHES AND A NORMALLY REVERSE-BIASEDDIODE SHUNTING SAID SERIES TUNED CIRCUIT.